July 24, 2008 -- Greater system complexity and ever-higher clock speeds continue to push IC power consumption to the limit. And though every generation escalates the demand on IC current, voltage levels drop due to steadily declining feature sizes on the silicon. Those lower voltage levels cause the power-supply noise margin (typically 5% from nominal) to shrink across the chips’ power-supply terminals. A noise level of 250mV might be acceptable for a 5-V power supply, but could be disastrous for a 1-V supply.

The objective of the power delivery network (PDN) is to provide stable power to the ICs. However, switching circuitry demands static and dynamic current, which across the PDN impedance causes the voltage to fluctuate at the chip’s power-supply terminals.

To effectively deliver power to the chip with minimal noise, the PDN’s input impedance should be below a specified design target over the entire frequency spectrum of interest, from dc to several hundreds of megahertz. A first-order design target for the PDN impedance is defined as the ratio of voltage tolerance to transient current. For example, for a supply voltage of 1V with 5% maximum allowable ripple and with the device drawing 5A of transient current, the target impedance is:

In theory, the PDN impedance from the chip’s perspective should be below this target up to at least the second harmonic of the fundamental switching frequency. Although a flat impedance profile in the frequency band of interest is desired, attempts are made to keep the PDN impedance below 10 m? up to 500 MHz (twice the fundamental frequency). This article discusses an intuitive Spice-based, system-level approach to planning, analyzing, and ultimately implementing the PDN layout scheme with a goal of meeting the target impedance within the defined frequency band.

By Jitesh Shah. (Shah s sn advanced packaging engineer within the Package Design Group at Integrated Device Technology, Inc.)