August 28, 2008 -- Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to guarantee interoperability when different memory devices are used together and that they work when powered up. Fundamentally, interoperability begins at the physical layer.
For a DDR memory interface, the responsibility of good physical-layer performance falls at the hands of the design engineers and implementers, whether they’re developing a DDR memory controller, chip, or system. Other standards such as USB, PCI Express, SATA, or fully buffered DIMM (FBD) have dedicated standard bodies that govern how to carry out compliance testing. DDR memory testing, on the other hand, is unique because JEDEC doesn’t enforce a compliance program—it expects adopters to perform the compliance measurements themselves.
One common measurement method for compliance testing is eye-diagram analysis. This method provides a comprehensive analysis of a DDR memory’s waveform signal integrity by looking at the eye characteristics. Through the eye diagram, you can quickly gauge the amount of jitter on the device, if there’s any glitch or non-monotonic edge, and other problems on the device.
This article will highlight some of the eye analysis methods you can find with the oscilloscope as well as the logic analyzer. It also discusses some of the debugging capabilities of the instruments when problems are found while performing eye-diagram analysis.
By Min Jie Chong. (Jie Chong is a product manager for Agilent Technologies, Inc.'s oscilloscope division.
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Design Magazine website.
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