October 7, 2008 -- Advanced process technologies (90nm, 65nm, 45nm and below) pose difficult power management challenges for chip designers. Exponential growth of leakage power can result in unacceptable increases in total power (leakage + dynamic), and standby power. Manufacturing variations can result in a wide distribution of minimum frequency and maximum power consumption across parts. Wide process distributions can prevent parts from achieving acceptable yields within a given power and frequency specification. Chip designers are challenged to choose between a standard process to meet performance goals or a low power process to meet total power or standby power goals.
By Dan Hillman. (Hillman is Vice President of Engineering, Transmeta Corp.)
This brief introduction has been excerpted from the original copyrighted article.