Verification planning is an essential part of the chip design process, yet experience shows that it is seldom attempted with any rigor. Enthusiasm for the task tails off rapidly as soon as the "real work" of coding the testbench becomes feasible. Limited knowledge of how to do effective verification planning, low personal motivation and benefits, and lack of permission are common reasons for abandoning the planning early. Subsequent verification tends to be inefficient, impacting both the quality of the design and delivery schedule, and leading to a stressful and unsatisfying project experience for all involved.
In this presentation, Dr. David Robinson from Verilab provides an introduction to Requirements Based Verification, a verification planning approach which aims for efficiency by allowing project stakeholders visibility into the size, scope, progress and risk of the overall verification process. Good risk-based visibility at all stages helps ensure that verification proceeds with few surprises.
Access the entire document on the Verilab, Ltd. website.
