October 16, 2008 -- There is intense pressure on all levels of chip engineering to reduce power consumption. That situation, in turn, has led to increasingly dramatic—and invasive—measures to reduce power in individual blocks and circuits. These efforts have been extremely successful, but they have come at a cost in design complexity—often the topic of conferences.
At least as serious, and much less discussed, there has been a serious impact on the verification process. At best, aggressive power management complicates functional verification. At worst, it can render a design unverifiable. EDN has spoken with design teams in the United States, Europe, and Asia to understand the scope of the problem in logic design and to see how the best designers are coping with the new verification challenge.
The most used logic-level power-management techniques fall nicely into a few categories, based on the obvious ways to reduce static and dynamic power. For static-power reduction, the only simple things you can do are to use high-threshold-voltage transistors as much as possible, reduce the voltage on the supply pins, or turn the supply off altogether. The techniques for accomplishing these tasks include multithreshold design, multivoltage design, and power gating.
For reducing dynamic power, your options are to reduce the supply voltage or reduce the frequency. Techniques for this process include clock gating and DVFS (dynamic-voltage-frequency scaling). This article will examine the impact of each of these ideas on verification.
By Ron Wilson, EDN Executive Editor
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.