This white paper describes some of the current problems associated with the design of high-density programmable logic devices, as well as solutions for addressing the problems by using Hier Design Inc.'s initial product, called PlanAhead.
Hier Design is developing and supporting silicon virtual prototyping software for the design of electronic systems based on high-density FPGAs. Silicon Virtual Prototyping is the process of providing a representation of the final design early in the design cycle to easily comprehend, modify, verify, and implement the design to achieve higher performance and better routability. PlanAhead enables the design of complex, high-density FPGAs with core technology, including a hierarchical floorplanner and analyzer.
PlanAhead seamlessly fits in to any existing design flow by interfacing with all available FPGA synthesis tools and by encapsulating all of the Xilinx ISETM Placement and Routing software ("PAR") commands. PAR can be run for individual blocks or for the entire design with the ability to modify results for better performance or fit. PlanAhead also provides powerful capabilities for incremental and modular design flow that no other product offers. PlanAhead will support all Xilinx high-end architectures including Virtex-II, Virtex-II Pro, and future architectures, as they become available.
