Ten years ago, the EDA industry faced a crippling divergence in timing between RTL synthesis and placement caused by rapidly rising wire capacitances relative to gate capacitances. Without some reasonable level of placement knowledge to give credible estimates of wire length it was becoming impossible to measure design timing with any accuracy during RTL synthesis. At this time, placement tools were not directly aware of timing and focused instead on metrics indirectly related to timing such as total wire length. As chip designs scaled to "deep sub-micron" geometries (180nm and 130nm), the change in timing around placement became so significant and unpredictable that even manual iterations between synthesis and placement no longer converged. The solution was to re-invent placement, making it both directly aware of timing and also weaving in many of the logic optimization techniques exploited during RTL synthesis, for example gate sizing and net buffering. This process was not easy, and ultimately saw a major turnover in the backend design tool landscape as a new generation of "physical optimization" tools were developed, released and proliferated throughout the chip design community.

Today timing is diverging once again, but for a different set of reasons (on-chip variation, low power, and design complexity] and at a different point in the design flow (CTS). While this divergence has so far received little media attention, this paper shows that the divergence is severe - so much so that we believe it is having a critical impact on the economic viability of migration to the 32nm process node. Clock concurrent optimization is a revolutionary new approach to timing optimization which comprehensively addresses this divergence by merging physical optimization into CTS and simultaneously optimizing both clock delays and logic delays using a single unified cost metric.