March 3, 2009 -- In not-so-distant past, less than 20% of high-end digital devices had any significant amount of analog /mixed-signal (AMS) content; by comparison, in the case of design starts in 2007, more than 80 percent of devices contain relatively large amounts of AMS. Today’s applications need digital processing coupled with analog to digital converters (ADC), digital to analog converters (DAC), Phased Locked Loop (PLL) and other analog IP’s.

Analog circuits are sensitive to layout, matching, proximity and demand attention to interface details such as signal swing, zero level, and drive impedance. This increase in analog content in System on Chip (SOC) and complexity of analog IP brings in new challenges slowing the progress towards fully functional first time right device. Several full chip design respins occur due to issues with analog IP. Difficulty with analog IP integration or reuse is widely recognized fact and there have been several discussions on this topic in various technical forums and conferences. However little methodology work is done for successful analog IP integration/reuse.

This article introduces detailed methodology guidelines for successful analog IP integration in SOC. The guidelines described in this paper are based on thorough root cause analysis of real design issues related to analog IP from several SOC designs. The knowhow of issues prior to design tapeout and ensuring compliance to guidelines listed in this paper had been successful in significantly reducing design re-spins and getting closer to fully functional first time right device.

By Pankaj Singh. (Singh is with Infineon Technologies India, Ltd.)