March 16, 2009 -- Advanced process technologies, such as 90nm, 65nm, 45nm and below, present significant power management challenges for high performance semiconductors.

Chip designers face increasing challenges in meeting performance and power goals. Advanced process technologies tuned for high performance semiconductors are implemented at the expense of substantial increases in active, average and standby power. Exponential growth in transistor leakage in these advanced processes widens the performance-power trade-off gap. Increasing transistor leakage, coupled with manufacturing variations, can result in wide distributions of minimum frequency and maximum power consumption results across chips. Chip designers are challenged to choose between standard processes to meet performance goals or low power processes to meet power goals.

This article describes a unique suite of power management, leakage control and process compensation technology geared towards reducing power while optimizing performance. This integrated solution, including advanced algorithms, innovative circuits, unique devices and structures, software and manufacturing optimization methods, will be discussed. Silicon performance results will be reported.

By Dan Hillman. (Hillman is with Transmeta Corp.)