Page loading . . .

  
 You are at: The item(s) you requested.Friday, May 24, 2013
IC Package to PCB Co-Design  
Publication: Printed Circuit Design & Fab
Contributor: Altium, Ltd.
 Printer friendly
 E-Mail Item URL

March 1, 2009 -- Many interesting assembly methods and packaging techniques have been explored in the past to overcome the challenges of trying to make more features fit in less space. One can say the printed circuit board itself was a revolutionary technology that enabled low-cost mass production of electronic equipment, well before semiconductors were put into widespread use. However, aside from the complexities of their production, PCBs presented a new set of challenges for engineers and manufacturers to overcome. Design in the consumer space, for example, was a constant tradeoff between size, look, function, user interface (psychology), power, reliability and yield. New interconnect technology required new packaging for components, which in turn required new assembly machinery and practices. Vacuum tubes for small appliances went to pig-tails rather than sockets, but their pin configuration was still largely dictated by the physical design of the plate, grid(s) and cathode within the envelope. New machines had to be created for the preparation and preforming of component leads, then along came the transistor. So the drive continues toward making things smaller, faster, better.

At each step of the way, the configuration of device pins has largely been dictated by the internal physical structure of the device in question. Even today, we still use many devices that have a pinout that, to the PCB designer, is far from sensible. When you consider the cost and complexity of the actual chip design and constraints of power consumption and timing, this is hardly surprising.

Another evolutionary step in the electronics industry was the development of MSI, LSI and then VLSI (medium/large/very large scale integration) COTS (common-of-the-shelf) components. Most notorious among these are the 7400 standard logic series and their pin-compatible descendants, as well as various transistor arrays and de facto standard analog parts like the 741 op-amp or the LM7805 regulator. Throughout the 1980s and 1990s, I used many of these components in designs, and I always lamented over the seemingly ridiculous pinouts of many useful devices that made my life difficult as a budding design engineer.

By Benjamin Jordan. (Jordan is a field applications engineer with Altium, Ltd.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the Printed Circuit Design & Fab website.

Read more about
Altium, Ltd.
on SOCcentral.com

Keywords: Printed Circuit Design & Fab, Altium, packages, packaging, PCB design, EDA tools,
590/28349 3/1/2009 5612 199


Designer's Mall
0.1875



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.265625