April 23, 2009 -- In simpler times, FPGA power consumption was a simpler issue. In the traditional applications of high-capacity FPGAs, such as expensive network routers, telecommunications switching gear, and prototype boards for ASIC designs, all you needed to know was how much peak power the FPGA could consume and how to provide cooling for its operating appetites. Today, the world is different.
"Previously, FPGAs were not a serious alternative for production," says Rahul Shah, director of customer solutions at design-services vendor eInfochips. "But with shorter life spans for products and more emphasis on time to market, we are seeing customers want to go into production with FPGAs. So, more focus is now going onto the power consumed in the FPGA."
Facing tight enclosures with minimal cooling, tight budgets, and sometimes even battery power, designers must be able to get accurate power estimates on their FPGA designs early in the design cycle. They must be able to refine those estimates throughout the cycle so that they can apply aggressive power-management techniques (Figure 1). And they must be able to accurately measure the power of the resulting design. As it turns out, none of these requirements is trivial.
By Ron Wilson, EDN Executive Editor
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EDN Magazine website.