May 25, 2009 -- This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC CPU cores. The cache has a number of novel features including advanced support for data prefetch, coherency, and performance monitoring. Results are presented showing the performance improvement profile over a large class of applications.
By Andrew Jones, Mark Hill, Mark Beaumont, James Pascoe, Stuart Ryan, and Robert Deaves. (All are with STMicroelectronics R&D, Ltd, Bristol, UK.)
This brief introduction has been excerpted from the original copyrighted article.