June 30, 2009 -- Power has risen to the No. 1 or No. 2 concern in contemporary engineering surveys as more devices—from medical equipment to cell phones to portable music players—go mobile. The solution, until recently, was simple: select an application-specific integrated circuit (ASIC) that engineers could optimise for power. The size of the potential market justified the up-front engineering costs because it would be amortized over hundreds of millions of units. But the frequency of that choice has declined in recent years. Consumers are demanding more features and functionality in their devices more quickly, and that shrinking product life cycle (with attendant smaller unit volumes) has squeezed ASICs as a solution.
As the spotlight has turned to the more flexible and fast time-to-market FPGA devices, the concern about the programmable device’s power history has become increasingly evident. But innovation has quickened in the programmable logic space. Gains in architecture and process technology have wrung out advances in performance and cost, yielded smaller, better packages, and reduced power consumption.
New device families now open a world of design choices for system engineers who no longer have to compromise on their power budgets when using a FPGA.
By Christian Plante. (Plante is Director of Marketing, Low-Power and Mixed-Signal FPGAs at Actel Corp.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Components in Electronics (CIE) website.
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