July 13, 2009 -- The design, verification and tapeout are complete, time to celebrate, to enjoy another successful design. At least until the silicon comes back. And then ...
If you are like most design teams at an advanced process node, the real work begins. For all our efforts, for all our tests, for all our EDA flows and tools, the majority of silicon is not correct the first time, or even the second or ... well you get the picture.
Why, when so much time and money is spent on verification, do we expect silicon re-spins, do we expect verification to fail us, do we expect delays in product launch? We have had generations of tools which enabled unprecedented improvements in time to market, design complexity and performance, but yet we stand at a precipice, an abyss, out of which many chips never appear.
What is it about the advanced process nodes that cause such failures? Have we pushed technology to a point where our ability to control performance, yield and reliability are non deterministic? Or are we at a point where the accuracy required for success demands more rigorous design methodologies? Could a more rigorous approach deliver quality silicon sooner by using parasitic extraction for advanced process nodes?
Generally, there are two extraction products in a designer's toolkit for today's advanced nodes; a field solver for high accuracy requirements and a pattern matching tool for high capacity and performance. By combining these products, expectations are all problems can be overcome.
A quick review of these technologies is required to understand their applicability to advanced nodes.
By Maxim Ershov and Dermott Lynch. (Maxim Ershov is chief scientist at Silicon Frontline Technology and Dermott Lynch is Vice President at Silicon Frontline Technology.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Electronic Engineering Times (EE Times) website.