OSCI has recently published their TLM-2.0 technology which provides for interoperability between SystemC models of electronic components whose primary interfaces are memory-mapped busses. This is a very important development in the ESL industry, but it does have some limitations. In particular, TLM-2.0 needs to be extended for some real memory-mapped buses, and TLM-2.0 is only applicable at high levels of timing abstraction: un-timed, loosely-timed and very approximately-timed models. These limitations are inevitable given that OSCI can only create technology that is generic in nature and not associated with any specific real component.

OCP-IP, as the publisher of a memory-mapped IP core interface, is able to address these limitations and has done so.

This paper describes the approach adopted by OCP-IP to providing SystemC modelling interfaces for a real memory-mapped bus family. TLM-2.0 has shown itself to be an effective and efficient base technology for all variants of OCP at all levels of abstraction, from cycle-accurate to un-timed. Furthermore, the nature of TLM-2.0 and its use as a base technology for everything means that bridges between different protocols or between different levels of abstraction are very easy and efficient. We even see that in a very large number of cases an OCP component is directly interoperable with the OSCI Base Protocol.

James Aldis, (Texas Instruments France), Mark Burton, (Greensocs, Ltd.,) Robert Günzel, (Greensocs, Ltd and TU Braunschweig,) and Herve Alexanian, (Sonics, Inc)