|Publication: Design & Reuse|
October 15, 2009 -- Nowadays, the usage of intellectual property (IP) cores has been an alternative to the increasing gap between design productivity and chip complexity of system-on-chip (SOC) designs. To support this approach, it is mandatory to deliver complete systems in short time-to-market. Thus, IP core design organizations must assure high=quality IP cores delivering, in short time frames. In the most of the cases, these cores are produced in a multi-project environment. Our work proposes an iterative process for developing IP cores with prototyping in FPGA in a multi-project environment, based on the mainly market standards as VSIA, RUP, PMBOK and RMM ones. The process was applied successfully in an organization context with many projects parallel development.
By Francielle Santos, André Aziz, Daniele Santos, Millena Almeida, and Edna Barros. (All are with Informatics Center, Federal University of Pernambuco, Recife, Brazil.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
|Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, system-on-chip, SoC, Design & Reuse, |
|590/30054 10/15/2009 5689 252|