October 26, 2009 -- As the process technology nodes keep shrinking, the variation of the design parameters transition, such as cell delays, becomes non-linear across different process, voltage and temperature (PVT) corners. As a result, we face the following problems during timing closure:
A path can be setup critical in one corner, and hold critical in some other corner;
A different set of timing paths can become critical in different corners.
We have tried to address these concerns with our unique concept of comparing the ratios of clock and data path cells across the PVTs.
By Sunit Bansal, Naveen Sampath Krishna and Ateet Mishra. (All are with Freescale Semiconductor, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
