December 4, 2009 -- In current SOC designing, clock gating is one of the most effective and primitive power-saving techniques utilized to save dynamic functional power throughout the chip. In designs, clock gating is done broadly at two different design-flow levels. At the RT level, you introduce clock gating into the architecture of the design. This clock gating ensures the switching off of the clock to a particular IP depending upon the active and inactive states of that IP. At the synthesis stage, synthesis tools introduce automated clock-gating cells at a fine granular level depending upon the clock gating constraints provided by the user to the tool. These synthesis constraints include defining the minimum and maximum number of registers in a register bank to be driven by a particular type of clock-gating cell.

This article targets the common erroneous practices that designers may use while implementing clock gating in SOCs. It details the problem that arises from these errors and also the method to counter these problems early in the design flow.

By Anubhav Srivastava and Neha Srivastava. (Srivastava and Neha Srivastava are design engineers with Inc.)