Page loading . . .

  
 You are at: The item(s) you requested.Wednesday, June 19, 2013
Preamplifier and Read-Channel Design Addresses Hard-Drive Goals  
Publication: EDN Magazine
Contributor: LSI Corp.
 Printer friendly
 E-Mail Item URL

December 3, 2009 -- As the capacity of hard-disk drives continues to increase, the burden on the system to reliably access data on the media also increases. For read accesses in particular, this challenge is creating the need for ever-more-complex signal-conditioning and signal-processing algorithms to recover the data from the ever-decreasing signal quality—that is, lower SNR (signal-to-noise ratio)—of information coming off the media. To make the situation even more challenging, price, power consumption, and speed trends are all moving in difficult-to-address directions. Cost and energy draw must continue to decrease, and the rate at which the data comes off the disk must increase from one generation to the next. All of these factors make for a difficult but rewarding design challenge.

By Harley Burger. (Burger is a fellow at LSI Corp., with a focus on designing and marketing approaches for hard-disk drives.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Read more about
LSI Corp.
on SOCcentral.com

Keywords: embedded system design, signal integrity, EDN Magazine, LSI,
590/30270 12/3/2009 4072 194
Designer's Mall
4th Of July countdown banner
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.234375