Publication: EE Times EDA Designline
Contributor: Synopsys, Inc.
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December 8, 2009 -- Escalating design size and complexity, more complex design-rule checks (DRCs), higher DRC rule count and increasing design-for-manufacturability (DFM) challenges are causing the physical verification turn around time (TAT) for the advanced nodes to explode. Prevailing physical verification flows are predominantly post-processing oriented, relying on post-GDSII modifications of the design. Not only do these flows lead to suboptimal results, but they can also induce expensive implement-then-verify iterations between the place-and-route and physical verification tools. Metal-fill insertion, a mandatory manufacturability step at the advanced nodes, exemplifies this issue.
By Steven Yang and Rahul Kapoor. (Yang is Director of Design, Aquantia, and Rahul Kapoor, is a group product manager, Synopsys, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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| | Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, EE Times EDA Designline, Synopsys,
| | 590/30278 12/8/2009 5218 226 | |
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