SOCcentral: Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications (Synopsys, Inc. 30498)

You are at: The item(s) you requested.

Wednesday, June 19, 2013

Low-Power USB 2.0 PHY IP for High-Volume Consumer Applications

Company: Synopsys, Inc.

Printer friendly

E-Mail Item URL

The USB protocol has become a pervasive standard in the world of computing and consumer electronics. While few design teams would today contemplate designing their own USB intellectual property (IP), this semiconductor IP is far from commodity silicon. Synopsys introduces a second USB 2.0 PHY IP product line (titled DesignWare® USB 2.0 nanoPHY), which has been further optimized for low power, area, manufacturing cost and system performance targeted to mobile and high volume consumer applications. This offers designers a choice of highly-differentiated USB PHY cores for 0.13-micron processes and below.

By Gervais Fong, Product Marketing Manager, Synopsys, Inc.

Access the entire document on the Synopsys, Inc. website.

E-mail Synopsys, Inc. for more information.

Read more about
Synopsys, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, DesignWare IP, intellectual property, cores, Universal Serial Bus, USB, low power design, low-power design, power analysis, power optimization, Synopsys,

205/30498 1/20/2010 4136 189

Add a comment or evaluation (anonymous postings will be deleted)

Designer's Mall

$4th Of July countdown banner$

0.234375

Search site for:
Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction

David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification

Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP

Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy

Mike Donlin
The Write Solution
Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?

Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search
SOC Design ASIC Design ASIC Verification FPGA Design CPLD Design PCB Design DSP Design RTOS Development Digital Design	Analog Design Mixed-Signal Design DFT DFM IC Packaging VHDL Verilog SystemC SystemVerilog