Design teams are turning to advanced and unified verification methodologies that leverage multiple technologies to handle the biggest verification challenges. Constrained random verification leverages compute resources and functional coverage technology to provide more testing with less test code development. Setting up a constrained random test environment, however, can seem like a difficult task, especially when you consider that environments need to be flexible, scalable, and reusable. The infrastructure for constrained random verification requires more planning and structure, but the benefits in the end are well worth the investment. This paper shows how to start performing constrained random verification quickly and easily with DesignWare VIP and VMM for SystemVerilog.