Page loading . . .

  
 You are at: The item(s) you requested.Thursday, June 20, 2013
Integration In the Other Direction  
Publication: EDN Magazine
 Printer friendly
 E-Mail Item URL

January 21, 2010 -- SOCs (systems-on-chips) have historically represented the Holy Grail for electronics because using these chips allows electronic systems designers to pack a lot of digital circuitry into a small area. Nevertheless, fine-line CMOS does not suit use in analog, power, and RF functions, and tiny CMOS transistors are prone to noise and leakage problems. Further, the dedicated mask set you need to make the chip can cost more than $1 million. You then must commit to that design until high-volume sales amortize its costs. For these reasons, it sometimes makes more sense to use separate chips rather than pack everything onto one.

Dave Robertson, vice president of analog technology at Analog Devices, advocates employing "smart partitioning" rather than dictating a dogma for either integration or "disintegration"—that is, moving functions onto other chips. "You have to look at each case and pick the smart thing to do," he says. "The smart thing to do in 2010 was not the same smart thing to do in 2007 and may not be the same smart thing to do in 2013."

By Paul Rako, EDN Technical Editor

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EDN Magazine website.

Keywords: embedded system design, system-on-chip, SoC, EDN Magazine
596/30597 1/21/2010 3366 233
Designer's Mall
4th Of July countdown banner
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options


Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Reducing Power
by Raising the
Level of Abstraction


David Pursley
Director,
Product Marketing
Forte Design Systems

Exec Viewpoint

The Many Faces
of Low-Power Verification


Ghislain Kaiser
CEO, Docea Power

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Odd Parity

Summertime and the Livin' Ain't Easy


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL?


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25