Page loading . . .

  
 You are at: The item(s) you requested.Sunday, May 19, 2013
A Nuts and Bolts Engineering Approach to Using Open Source IP  
Publication: EE Times Embedded
Contributor: MindTree, Ltd.
 Printer friendly
 E-Mail Item URL

January 25, 2010 -- In the world of product development, time-to-market keeps shrinking and demand for better quality keeps growing. Open Source, which is often thought to be the definitive solution to meet both objectives, i.e., faster development cycle and better quality, is on the mind of many OEMs and product companies.

In reality, the companies find it difficult to overcome the FUD (Fear, Uncertainty and Doubt) to make a final decision and say, "Yes, we will use open source in our product."

In the product-development process, at the one end are the engineering people — developers, architects, engineering managers — who are aware of open source and its benefits, but lack the power to take decisions. At the other end, are the management and the legal people, who can take decisions, but may not have sufficient ground-up information. How do we bridge this gap? How can the engineering team convince the management to boldly embrace open source?

In this article I will go over some key factors and guidelines to consider with respect to the use open source in product engineering. The objective is for us, the engineering people, to be prepared with sufficient and solid information to convince our management and legal departments to take that final call with confidence.

By Girish Managoli. (Managoli is Senior Technical Manager at MindTree Research, Ltd.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Embedded website.

Read more about
MindTree, Ltd.
on SOCcentral.com

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, IP, intellectual property, cores, MindTree, EE Times Embedded,
596/30624 1/25/2010 2727 214


Designer's Mall
0.140625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25