February 23, 2010 -- Most semiconductor giants are cutting down on manufacturing costs by conserving on the die area. Fewer metal layers for interconnects saves additional mask-generation expenses. It also saves the manufacturing time in a semiconductor fab, thus shrinking the time to market for a device, which gives a significant competitive edge over other competitors.

Diminishing die sizes, fewer interconnect layers, and packing more and more IP blocks for high-end applications all pose greater design challenges and result in a very common phenomenon in physical design called congestion. A very high degree of congestion may render the design unroutable and, hence, inhibit design convergence. Congestion issues create one of the most difficult bottlenecks in design closure and should be spotted and tackled during the early phase of the physical design cycle.

This article sums up the most important among the many reasons for design congestion. It also explains why some of the most trivial-looking requirements can add to congestion if not taken care of. This article also presents some of the classic and some customized solutions for mitigating congestion in sub-90-nm SOCs. Finally, this article encompasses some important dos and don’ts for relieving congestion and ensuring a smooth transition through the physical design cycle.

By Abhishek Roy. (Roy is a design engineer at Freescale Semiconductor India.)