March 31, 2010 -- You work in an environment where demanding design goals and aggressive project schedules go hand-in-hand with the push to get more complex products to market faster. And you have just finalized the RTL description of your company's next-generation product, a large system-on-chip (SOC). With just a few weeks remaining for final synthesis, place-and-route and post-layout verification tasks, you wonder: can I still finish the job on schedule?
The answer depends on whether your synthesis solution is capable of delivering the best-possible quality-of-results (QoR) to meet all your timing, area, power and test requirements. Excellent QoR from synthesis is paramount to meeting your design objectives and cannot be compromised along the way.
Synthesizing a netlist with the best QoR, however, is no longer enough to ensure fast design closure and a predictable schedule. As process geometries shrink to 65nm, wire lengths and cell placement have a greater effect on critical timing paths in a design, leading to divergence of QoR between synthesis and place and route. The resulting uncorrelated design will invariably require changes to the layout (and often the RTL code itself) to meet your design requirements across all corners and modes of operation. And even if synthesis results are correlated, severe routing congestion can make it difficult to route the design. Design closure in this case will likely require extensive design alterations and successive iterations to converge to a routable design that also meets your performance specifications.
It is this convergence process—the numerous, time-consuming design iterations encompassing the entire implementation flow—that makes up most of the total implementation time and poses the greatest risk to your project schedule. A robust synthesis solution, therefore, must be capable of producing results for timing, area and power that are correlated with place-and-route results, and that minimizes the occurrence of routing congestion.
By Eyal Odiz. (Odiz is Vice President of Engineering, RTL synthesis and test automation at Synopsys, Inc.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
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