April 15, 2010 -- Today's complex silicon-on-chip (SOC) designs contain multiple instances of silicon intellectual property including CPUs, DSPs, and large numbers of interface IP to store and route video, audio, and data within these designs. On some large SOCs, as much as 85% of silicon real estate is made up of third-party IP. Given the time-to-market constraints, chips specially destined for consumer electronic devices, the standardization of individual interface IP blocks has made it very attractive to do a make versus buy decision. This has created a large and steady demand for interface IP from third-party suppliers. The expectations of quality for first time success, however, are extremely high.
Beyond shortening time-to-market, the advantage third-party IP provides SOC designers is reducing the design resources needed to build a large system on a chip while mitigating risk. To deliver these benefits, IP blocks must be as close to plug-and-play as technically possible, considering the variability in complex SOC designs. The worst-case scenario for a customer purchasing an IP block with an error is having to divert resources from the larger SOC effort to help find the problem, and even worse, being delayed in getting the chip into silicon. Hence, pre-silicon verification is extremely important to ensure against a costly respin of the SOC. Silicon-proven Interface IP blocks are less likely to cause this problem than those with little or no history. Successive generations of a given interface IP block builds on existing extensively debugged RTL code, hence maintaining the quality is desired.
The key element of a successful IP block is being able to seamlessly integrate into a larger design, especially with the myriad of internal buses. Seamless integration demands that the interface IP deliverables come with support that understands the SOC's operation in the final consumer application. For example, the support team should have a comprehensive understanding of the USB, SD/ SDIO, or MIPI specification as well as internal buses like AXI, AHB, APB, PCIe, PCI, etc. and how the IP block will behave within many different SOC environments, such as cell phone, netbook, video game, digital camera, and the many other consumer products being developed. In addition, the IP blocks must be customizable and verifiable to accommodate the unique requirements of individual customers.
By Somnath Viswanath. (Viswanath is with Arasan Chip Systems, Inc.)
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