June 10, 2010 -- As process geometries have scaled, design teams have used more and more of the additional silicon real estate available on chips to integrate embedded memories that serve as scratch-pads, FIFOs and caches to store data for the computational cores. These embedded memories allow for significantly better system performance and lower power compared to a solution where off-chip memories are used. As a result, most current designs have over 50% of their area used by embedded memories and these memories account for 50% to 70% of the total SOC power dissipation. Clearly, any attempt to reduce SOC power is incomplete if it does not attempt to reduce the power consumed by the embedded memories in the design.
Most of the embedded memory is single port SRAM, which provide single clock, read and write cycle operation. However for higher through-put applications single-port RAM are replaced by dual-port RAM which results in higher area and more power consumption. Also, IPs are designed for wide image size (Full HD) but in general, only the regular size (QVGA or HD) image applications are only used. This lead to under utilization of embedded memories as there is no way to switch off the un-used segment of the memory.
In this article we discuss an optimized power aware architecture named as "Cluster Memory Architecture". This architecture is implemented in design and development of 60 fps super scalar IP which can convert 60 VGA Frame to Full HD Frame per second. This architecture ensures similar or reduction of power consumed for same size single-port SRAM memory and similar performance as dual-port RAM. This architecture also facilitates for switching off the un-used segment of the memory.
By Akhilesh Mahaja, Naveen Tiwari and P. Raghuram. (All are with theASIC Design Group, DS India Labs, Samsung India Software Operations.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.