August 12, 2010 -- The search for productivity in SOC (system-on-chip) design is a search for balance between abstraction and automation. Greater abstraction at a step in the design flow means fewer design elements to process. Greater automation means that each element requires less human attention. Ideally, designers could capture an abstract representation of an SOC's intended behavior, verify that the representation describes the desired chip, and push a button to tape-out. We are not yet there.

For years, some enthusiasts have promoted high-level design languages—often dialects of C—as the path to greater abstraction. Except in a few categories of architectural elements, however, it has been difficult to move the design beyond behavioral or transaction-level representation and into the implementation flow. “High-level synthesis is still very domain-specific,” says Ken Wagner, PMC-Sierra's vice president of engineering. Without synthesis, designers must recode the high-level version by hand into RTL (register-transfer-level) logic.

While EDA vendors were struggling with synthesis, another kind of high-level abstraction had become common in SOC design: IP (intellectual-property) reuse. You would not ordinarily think of reusing IP as a high-level design method; it's a simple matter of expediency. The technique is so ubiquitous that many of today's SOCs simply couldn't exist without it. "In our shorter designs, often 80 percent of the chip is composed of IP," says Jitu Kahne, Director of Central Engineering at AppliedMicro.

By Ronald Wilson, EDN Executive Editor