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 You are at: The item(s) you requested.Tuesday, May 21, 2013
Use XML to Build ASIC or SOC Design Specifications  
Publication: EE Times Embedded
Contributor: SiBEAM, Inc.
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July 31, 2010 -- In a semiconductor company, the ASIC engineers design the hardware, and the hardware specification is distributed to other teams for hardware validation, embedded software development, and data-sheet documentation. Unfortunately, no standardized tools to document and distribute the specification exist. ASIC engineers often use common tools, such as Microsoft's Word or Excel, or even a plain text editor; these "tools" have many shortcomings when used to create a hardware specification.

First, these tools cannot easily convey the structure of a hardware specification. The hardware design of a chip typically has a tree-like hierarchy — the chip has several logical blocks, each block contains many registers, and each register has multiple bitfields.

In a Word document, to show the hierarchical relationship between data, a significant amount of formatting using headings, tables, fonts, and highlights is needed. Formatting this type of content is tedious and repetitive. The main problem, however, is the difficulty in extracting data from the specification created from these common tools.

Karen H. Wang. (Wang is a senior embedded software engineer at SiBEAM, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Embedded website.

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SiBEAM, Inc.
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Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, XML, system-on-chip, SoC,SiBEAM, EE Times Embedded,
596/31988 7/31/2010 1142 155


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