August 29, 2010 -- Many sources of yield loss, including out-of-spec equipment, incorrect handling of material, photomask defects, design-process sensitivities, library marginalities, and test issues, can occur during semiconductor manufacturing. The challenge at nanometer geometries is to quickly identify what caused the yield loss so that corrective action may be instituted. A yield problem that is not quickly eliminated erodes product margins and may make the difference between profit and loss. Manufacturing test combined with diagnosis-driven yield analysis can hasten the discovery of the root cause of yield loss or reveal that a yield problem exists.

To simplify manufacturing test and the process of generating test patterns, design-for-test (DFT) structures, such as scan chains, are incorporated into digital semiconductor devices. Scan diagnosis leverages the DFT structures and ATPG patterns, along with the design description and fail information from the tester to identify the location and type of defect most likely to be causing failures. By using logical path tracing and simulation techniques, the diagnosis tools identify a ranked list of suspected defects. The quality of diagnosis results is typically measured by accuracy and resolution. Scan diagnosis has long been a staple of physical failure analysis (PFA) labs and has more recently become a way of leveraging the design data for yield learning, a process called diagnosis-driven yield analysis (DDYA).

Implementing certain best practices helps the product engineer to get the most value out of DDYA at the lowest cost. The goals are to identify the defect mechanism that caused an excursion, identify a previously unknown systematic yield limiter, or pick the best die to submit to the PFA lab for root-cause identification. The main optimizations in any DDYA process include writing the test program, minimizing test time for the data collection, increasing diagnosis throughput, and reducing time spent performing the yield analysis.

By Chris Schuermyer. (Schuermyer is a product lead in the Silicon Test Solutions group at Mentor Graphics Corp.)