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Hunting that Elusive Bug  
Publication: EE Times EDA Designline
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September 28, 2010 -- This article discusses the non-trivial challenge of detecting and correcting the often elusive functional defects that unavoidably arise in the design of complex system-on-chip (SOC) devices. How do we mitigate the conflict between the dramatic increase in SOC design complexity and the need to deliver the design in a shorter time with the same or better design quality?

Clearly, we need new design and verification methods, and we need "all hands on deck" to develop them. That's why a consortium of six companies and six research institutes set up the Herkules project, with support from the German government. Over the past three years, this project teamed design and verification engineers from leading chip companies and developers of commercial verification tools from EDA companies, together with leading technology research institutes. Their goal was to develop a right-first-time verification approach for large digital and mixed-signal designs — and to ensure that it is widely applicable to the development of automotive and telecommunication systems that must comply with very high quality standards.

By Roland Syba. (Syba is a development engineer at Melexis GmbH in Erfurt, Germany.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, debug, debugging, verification, EE Times EDA Designline,
596/32257 9/28/2010 1166 195


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