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How to Reduce Board Management Costs, Failures, and Design Time  
Publication: EE Times Programmable Logic Designline
Contributor: Lattice Semiconductor Corp.
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October 12, 2010 -- In order to meet the demands of increased functionality, performance, and reduced power, many modern circuit boards use highly integrated CPUs, ASSPs, ASICs, and memory devices to implement the circuit board’s main function (the payload function).

Boards of this complexity are particularly common in equipment designed for communications infrastructures, computer servers, and higher end industrial and medical systems. Because the ICs on the board are usually fabricated with fine transistor geometries, they require multiple power supply rails with tight tolerances to operate. Typically, seven to ten supplies are needed in a complex circuit board, with higher numbers not unusual.

The management of these supplies — along with other system management tasks — is increasing in complexity and cost. This is leading many board designers to ask: "How can I reduce the cost and complexity associated with implementing board management?"

By Shyam Chandra. (Chandra is with Lattice Semiconductor Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Programmable Logic Designline website.

Read more about
Lattice Semiconductor Corp.
on SOCcentral.com

Keywords: FPGAs, field programmable gate arrays, FPGA design, PCB design, EDA, EDA tools, electronic design automation, EE Times Programmable Logic Designline, Lattice Semiconductor,
596/32440 10/25/2010 1217 175


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