Page loading . . .

  
 You are at: The item(s) you requested.Tuesday, May 21, 2013
Signal and Power Integrity Limitations for Mobile Memory In 3D Packaging: Part 2  
Publication: EE Times Memory Designline
Contributor: Rambus, Inc.
 Printer friendly
 E-Mail Item URL

October 11, 2010 -- In a first set of simulations, the impact of Inter Signal Interference (ISI) and crosstalk on the eye opening of the data channel was investigated. For the ISI simulation, only the victim signal is transmitting while all other signals are kept quiet. For crosstalk simulations, all signals are transmitting data, however, the data pattern transmitted by the aggressor lines is different from the data transmitted on the victim line. All simulations use an ideal power supply for the transmitter and the receiver of the interface system. In order to achieve the best possible performance in this system, a nearly optimal PCB routing was assumed with minimum crosstalk. PCB signals were routed as striplines with a large spacing of 3w (three times the width of the signal line itself) between adjacent lines.

By Ralf Schmitt, Joong-Ho Kim, June Feng, Dan Oh, and Chuck Yuan. (All are with Rambus, Inc.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Memory Designline website.

Read more about
Rambus, Inc.
on SOCcentral.com

Keywords: ASICs, ASIC design, PCB design, 3D ICs, 3D chips, stacked ICs, packages, packaging, power integrity, signal integrity, noise, EE Times Memory Designline, Rambus,
596/32441 10/25/2010 1095 142


Designer's Mall
0.15625



Copyright 2002 - 2004 Tech Pro Communications, P.O. Box 1801, Merrimack, NH 03054
 Search site for:
    Search Options

Subscribe to SOCcentral's
SOC Explorer
Newsletter
and receive news, article, whitepaper, and product updates bi-weekly.

Exec Viewpoint

Maximizing the Value of Your Internal IP


Warren Savage
CEO, IPextreme

Exec Viewpoint

Yes, Virginia,
There Is a
Stitch-and-Ship


Dave Johnson
VP of Sales
Breker Verification

Odd Parity

Lets' Go On
with the Show!


Mike Donlin
The Write Solution

Odd Parity Archive

Barbara's Bytes

So, Just What
Is ESL


Barbara Tuck
Senior Editor,
SOCcentral

SOCcentral Job Search

SOC Design
ASIC Design
ASIC Verification
FPGA Design
CPLD Design
PCB Design
DSP Design
RTOS Development
Digital Design

Analog Design
Mixed-Signal Design
DFT
DFM
IC Packaging
VHDL
Verilog
SystemC
SystemVerilog

Special Topics/Feature Articles
3D Integrated Circuits
Analog & Mixed-Signal Design
Design for Manufacturing
Design for Test
DSP in ASICs & FPGAs
ESL Design
Floorplanning & Layout
Formal Verification/OVM/UVM/VMM
Logic & Physical Synthesis
Low-Power Design
MEMS
On-Chip Interconnect
Selecting & Integrating IP
Signal Integrity
SystemC
SystemVerilog
Timing Analysis & Closure
Transaction Level Modeling (TLM)
Verilog
VHDL
 
Design Center
Whitepapers & App Notes
Live and Archived Webcasts
Newsletters


About SOCcentral.com

Sponsorship/Advertising Information

The Home Port  EDA/EDA Tools  FPGAs/PLDs/CPLDs  Intellectual Property  Electronic System Level Design  Special Topics/Feature Articles  Vendor & Organization Directory
News  Major RSS Feeds  Articles Online  Tutorials, White Papers, etc.  Webcasts  Online Resources  Software   Tech Books   Conferences & Seminars  About SOCcentral.com
Copyright 2003-2013  Tech Pro Communications   1209 Colts Circle    Lawrenceville, NJ 08648    Phone: 609-477-6308
1  0.25