November 17, 2010 -- To achieve higher quality on today's multimillion-gate designs and high-speed ASICs, structured DFT (design-for-test) methodologies such as scan, at-speed test, scan compression, and BIST (built-in self test) have become the most important features for manufacturing test. Typically, testability issues are detected at the very last stage of the design flow during ATPG (automatic test-pattern generation) or gate-level simulation. This stage is very close to tape-out, and it becomes necessary to fix the original RTL (register-transfer-level) design for re-use and testability and then repeat the steps of the implementation flow, a process that can have a large impact on the project schedule.

Many design teams have adopted static verification checks and methodologies to catch testability issues early at RTL for both stuck-at and at-speed testing. Yet, the connectivity of different IP blocks at the SOC level-with respect to memory BIST, 1149.1 JTAG, or IEEE 1500 standards-is mainly verified through functional simulation. Test benches are not always the best solution for verifying connectivity of the logic at the SOC level with signals from SerDes, PLLs, IEEE 1149.1/1500 circuits, and BIST logic that go to various blocks in the design.

[But] there are several general disadvantages to using functional simulation for verifying connectivity.

By Marco Brambilla, Jean Philippe Loison and Kiran Vittal. (Brambilla is a design manager at STMicroelectronics and Loison is a design engineer at STMicroelectronics; Vittal is a product marketing director at Atrenta, Inc.)