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Analog Design Quality Closure: What's Missing from Current Flows?  
Publication: EE Times EDA Designline
Contributor: Satin Technologies
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December 6, 2010 -- The design of AMS circuits requires the adoption of specific recipes, the sharing of past experiences, and a huge number of design explorations with different constraints and parameters. The quality of results and the time to closure in analog designs largely depend on the know-how and experience of the engineers. Analog designers use dedicated implementation and verification tools during the different steps of the design flow and take decisions for the next steps based on the analysis of the results, driven by their skills and experience.

Although analog-design best-practices have traditionally been viewed as not being as sharable as digital design — as being more manual, creative, ad hoc — more and more of the repetitive and manual, tedious tasks are being automated to enable designers to focus on key areas. The increase in size, complexity, and automation of the AMS design process makes it even more important to leverage the gained experience on a given design and to convey the best practices from project to project, to continuously build a know-how data repository that can be shared and reused efficiently across an organization. In addition, some specific metrics also can be used to qualify third-party analog intellectual property (IP) and to help formalize the communication of expectations between providers and integrators to ensure that quality assessment is fact-based.

Ad hoc quality monitoring and manual checklist assessment usually are considered as brakes to methodology and best practices adoption because of the risk of subjective and/or wrong statements as well as intrusion and delay in engineering tasks. This article presents the implementation of an objective, automated and flexible quality assessment process. Examples are used to describe process implementation and results. It describes how the best practices and quality metrics identified and used by analog specialists can be turned into formalized rules, how these rules can be automatically assessed from the analog design flow state and how the assessment results can be continuously shared between the different stakeholders. The approach enables the creation of a holistic quality-monitoring cockpit on top of the analog design ecosystem, easily configurable and adaptable, with no intrusion into the design flow and no addition to engineering overhead.

By Stephane Bonniol. (Bonniol is R&D Director at Satin Technologies.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times EDA Designline website.

Read more about
Satin Technologies
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Keywords: ASICs, ASIC design, analog design, EDA, EDA tools, electronic design automation, Satin Technologies, EE Times EDA Designline,
596/32729 12/6/2010 883 170


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