December 13, 2010 -- As technology continues the trend to smaller geometries, various challenges arise to delivering silicon on time. One of the critical areas is parasitic extraction, where the standard extraction tools, which are based on pattern-matching algorithms, are unable to deliver the accuracy required to ensure quality silicon. There are a number of reasons for the failure and the need for a more robust 3D solution.

• Device model changes — As more advanced process nodes are introduced, it is necessary to improve the quality of device modeling. As a result of these improvements, there is the need to remove extrinsic interconnect parasitic models from the device model. Specifically, gate poly-to-contact capacitance must become part of interconnect parasitic extraction. Unfortunately for mainstream extractors, these models are 3D in nature, and as a result, yield unacceptable errors in pattern matching extractors.

  Other structures around devices are also 3D in nature, but the gate-to-contact capacitance dominates errors. A fundamental problem is that capacitance is a strongly nonlinear characteristic with respect to the boundary condition, and so the proximity of the metal layers and contacts/ vias to the device may alter the device's "intrinsic" capacitances. The "boundary" between the device-related capacitances and parasitic interconnect capacitances is blurred, or ill-defined. In this situation, it is extremely important to achieve a good consistency between the device model and interconnect parasitic extraction settings in order to avoid capacitance double-counting or omitting.

• Cell-level 3D structures — As dimensions of cells and the dimensions between cells shrink, the magnitude of coupling capacitance between devices (e.g., diffusion-diffusion) increases in relative magnitude. Some pattern-matching extractors ignore these capacitances as their models are optimized for inter-cell routing parasitics. As greater focus is made on the quality of intra-cell parasitics, these modeling gaps or heuristics have shown increasing relative error.
• Wire spacing — Pattern matching extractors have larger errors as spacing increases between wires. The manufacturing recommendation of increasing wire spacing to improve yield, results in larger errors in mainstream extractor results.
• DFM contact/via doubling — In addition to wire spacing, contact/via doubling also naturally enhances the 3D nature of interconnect routing, particularly in the vicinity of metal 1. The combination of nearly twice as many contacts/vias and hammerhead landing pads provides pattern matching tools with another accuracy challenge.
• Multi-finger devices — MOS transistors with large gate widths are normally laid out so that they occupy approximately a square-like area. This is achieved by fracturing devices into smaller sections (fingers) and wiring them in parallel. Multi-finger devices allow lower gate resistance (important for high-speed and RF applications) and smaller parasitic capacitances. Extraction of parasitics in multi-finger devices is a challenge. Standard extractors have problems in dealing accurately with such effects as distributed nature of the devices along the gate width, three-dimensional capacitive coupling between gate and source-drain and bulk contacts, substrate resistance network, and correct connectivity between active devices and parasitic RC network. Failing to consider accurately these effects leads to significant errors (as high as 30 to 40 percent) in both dc and ac device characteristics.
• Passive devices (MIM/MOM/PIP caps) — Capacitance-extraction tools may be used for calculation of not only parasitic capacitance between the nets, but also "useful," intended capacitances of inter-digitated capacitors formed by metal interconnects (these capacitors are also called VPP — vertical parallel-plate capacitors, comb capacitors, MOM [metal-oxide-metal] and so on). But foundries do not normally provide process design kits for MOM capacitor calculation. As a result, the design of integrated capacitors is based on a time-consuming and expensive trial-and-error method. Electromagnetic field solvers can be used to calculate MOM capacitor characteristics, but the simulations are very slow (typically, one simulation run requires tens of hours or even days to complete). Because of this, the capacitance-extraction tools should calculate intended capacitance, parasitic coupling to neighboring nets and frequency-dependent characteristics for RF applications, such as quality factor and resonant frequency.
• Resistance extraction — Resistance extraction of interconnects is a significant part of parasitic extraction. Popular extraction tools rely on simple geometric fracturing of metal nets, assuming a one-dimensional current flow, and subsequent generation of resistive network. This approach works for long narrow wires, but fails if the current flow is non-one-dimensional. Fracturing of metal nets for resistance extraction should be based on a more physical approach that accurately captures effects such as current crowding, current flow in diffusion areas and multi-finger devices, and interaction of the current flow in interconnects and in active devices.

As has been the tradition in EDA, the leading-edge problems are typically solved by start-ups. As is always the case, new challenges will arise, but at least in EDA, new start-ups will provide innovative solutions, helping move the market past the limitations of today's standards. Silicon Frontline Technology is providing a product, F3D, to address these issues and is being used and endorsed by leading foundries, leading integrated device manufacturers (IDMs) and fabless companies.

By Dermott Lynch.

Dermott Lynch is Vice President of Sales and Marketing at Silicon Frontline Technology, Inc. He has been involved in several start-ups including Nassda, Sente and Quad Design.