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Debugging for Power Consumption  
Publication: New Electronics Magazine
Contributor: IAR Systems AB
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January 10, 2011 -- Power consumption has traditionally been something influenced only by hardware developers. But power consumption depends not only on the hardware, but also on how it is used and how it is controlled by the system software. Through power debugging — coupling source code to power consumption — it becomes possible to test and tune for power optimization.

The approach is based on the ability to sample power consumption and to correlate each sample with the program's instruction sequence and, hence, with the source code. One difficulty is achieving high sampling precision. Ideally, power consumption should be sampled at the system clock's frequency, but power system capacitances reduce the reliability of such measurements. From the software developer's perspective, it is more interesting to correlate power consumption with source code and various events in the program execution than with individual instructions, so the resolution needed is much lower.

By Lotta Frimanson and Anders Lundgren. (Both authors are with IAR Systems AB.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the New Electronics Magazine website.

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IAR Systems AB
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Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, embedded systems, embedded system design, EDA, EDA tools, electronic design automation, low power design, low-power design, power analysis, power optimization, software development tools, debug, debugging, New Electronics Magazine, IAR Systems,
599/32896 1/10/2011 1281 186


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