SOCcentral: Meeting Timing Specs on Boards with Picoseconds of Margin (EE Times Signal Processing DesignLine 33019)

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Sunday, May 19, 2013

Meeting Timing Specs on Boards with Picoseconds of Margin

Publication: EE Times Signal Processing DesignLine
Contributor: Mentor Graphics Corp.

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January 19, 2011 -- Length-match your traces to within 100 mils. Or is it 10 mils? Or should you go down to 1 mil? Should you include the lengths of the vias? How about the lengths of resistors? Understanding the origin of length-matching requirements, coupled with some rudimentary signal integrity analysis, can help answer these questions.

Determining length requirements requires an understanding of flight time, electrical length vs. physical length, loading and signal quality. Those elements are vital in determining what the length really needs to be, as well as in determining the allowable trade-offs to meet system timing goals.

By Patrick Carrier. (Carrier is a technical marketing engineer for high-speed PCB analysis tools at Mentor Graphics Corp.)

This brief introduction has been excerpted from the original copyrighted article.

View the entire article on the EE Times Signal Processing DesignLine website.

Read more about
Mentor Graphics Corp.
on SOCcentral.com

Keywords: PCB design, EDA, EDA tools, electronic design automation, timing analysis, timing optimization, timing closure, Mentor Graphics, EE Times Signal Processing DesignLine,

599/33019 1/19/2011 1073 167

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