| Verification Challenges and eDFM in Digital Designs | Publication: DAC Knowledge Center Contributor: Mentor Graphics Corp.
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January 5, 2011 -- In the past decade, the term "DFM" (design for manufacturing) was a massively used semiconductor industry buzzword. In reality, different people interpreted DFM to have different meanings. Some people thought of resolution enhancement technologies (RET) used in the creation of lithography masks for IC fabrication. Others viewed DFM from the design and physical verification side, which involved techniques such as critical area analysis, critical feature analysis, metal fill, litho hotspot detection, etc.
In recent years, another buzzword was introduced: electrical DFM or "eDFM." Although it includes the general term, DFM, the added "e" makes it a more-specific definition referring to the electrical effects of manufacturing variation on parametric yield. For a designer, eDFM makes intuitive sense because it translates complex manufacturing concerns into a meaningful electrical property that he or she can understand and may be able to control. This articler looks at eDFM for digital designs.
By Hazem Hegazy. (Hegazy is with Mentor Graphics Corp.)
This brief introduction has been excerpted from the original copyrighted article.
Read more about Mentor Graphics Corp. on SOCcentral.com |
| | Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, design for yield, design-for-yield, DFY, Mentor Graphics, DAC Knowledge Center,
| | 599/33080 1/5/2011 1022 115 | |
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| | 0.15625 |
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