January 11, 2011 -- Fueled by massive functional capacity, high-performance and low-power silicon processes, and exploding software application content, the pace and scope of electronics innovation is accelerating. The challenges of forging increasingly complex systems are also growing, confronting traditional approaches with out-of-control verification costs and missed market windows. What's needed is a system-design approach that allows both earlier software development and faster silicon development, along with earlier and more frequent system-integration steps.

This methodology must enable a unified hardware/ software-development and verification environment, and allow the specification, analysis, and verification of constraints such as timing and power in the context of the software and the system. This article highlights recent advances in system design, transaction-level verification, and software development that support such a unified environment. The article discusses the role of standards and explains the productivity gains behind a transaction-level modeling (TLM)-to-GDSII design and verification flow.

By Steve Brown and Raj Mathur. (Brown is the Director of Marketing for Enterprise Verification Process Automation and Mathur is Senior Product Marketing Manager in Cadence Design System, Inc.'s System Design & Verification Product Management team.)