| Ease Production at 65nm with DFM | Publication: EE Times EDA Designline Contributor: Mentor Graphics Corp.
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February 15, 2011 -- The challenges of production at advanced process geometries are well-known. In anticipation of reaching today's leading-edge process nodes, electronic design automation (EDA) companies and chip foundries have been developing and perfecting design-for-manufacturing (DFM) technology to address users' critical needs. However, many designers viewed these DFM tools with skepticism as they continued to get products to market without them.
Two new factors now influence the use of DFM for IC development at 65nm and below. First, foundries now require or strongly recommend DFM checks, essentially equating them to traditional design rule checks. This requirement implies a shift in responsibility; customers not employing DFM checks during design verification may find the foundry less willing to address yield issues when the product goes into volume manufacturing. Second, some companies have discovered that DFM can be a source of competitive advantage, and are aggressively deploying it to wring more performance out of and/or increase reliability of their designs at leading-edge process nodes.
By Jean-Marie Brunet, Mark Redford, Colin Thomas and Mark Scoones. (Brunet is Director of DFM Product Marketing for Mentor Graphics Corp.; Redford is General Manager, North American Operations, Thomas is responsible for DFM technologies and Scoones is responsible for digital physical design at Cambridge Silicon Radio.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the EE Times EDA Designline website.
Read more about Mentor Graphics Corp. on SOCcentral.com |
| | Keywords: ASICs, ASIC design, custom IC design, EDA, EDA tools, electronic design automation, design for manufacturing, design-for-manufacturing, DFM, EE Times EDA Designline, Mentor Graphics,
| | 599/33261 2/15/2011 1090 153 | |
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| | 0.15625 |
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