February 25, 2011 -- Thru-silicon vias (TSVs) have become a very hot topic in in recent months. Ever since Xilinx reported that it is using a 2.5D TSV approach for its Virtex-7 FPGAs, the industry started to salivate with the prospects of this new technology. While this technology may be accessible for larger stacked memory, FPGAs, MEMS devices, and CMOS image sensors, this does not inherently mean it is ready for ASIC applications. Before we get into some of the details, it is important we take a moment to calibrate with the terminology used in this space.
- 2.5D - Refers to having one or several die mounted to another inactive die with thru-silicon vias in order to route nets between the active die and to the substrate.
- 3D-IC - Refers to one or several die mounted to the backside of an active silicon die through these TSVs
- Glass interposer - A die made of glass with vias that connect both sides of glass die together for signal/ power transmission.
- Silicon interposer - A die made of silicon with vias that connect both sides of glass die together for signal/ power transmission.
- Tile - A die mounted to a glass-interposer, silicon interposer or 3D-IC. These generally have microbump pitches of 30 - 80Ám.
- TSV - Thru-silicon via, a via that connects two opposite sides of a silicon die/wafer. (See Figure 1.)
Figure 1. Cross Section of TSVs. Source: P. Leduc, LETI, D43D, 2010.
EDA tool infrastructure
The market for the design of 3D-IC and 2.5D interposers really started with several niche players making stand-alone tools to address this need. Most of these are on open-architecture platforms so they share data with some other EDA tools. It is not clear if these niche EDA tool companies will gain significant market share before the larger EDA tool companies have a chance to surpass them. At least one of the major EDA tool companies is already presenting a solution at tradeshows. The lack of design kits from the wafer fabs has given these large EDA companies a chance to catch up and apply their greater resources to enter this 3D-IC and 2.5D design space.
One interesting observation I made after seeing some of these tools in action is that they appear to be built on package-design platforms instead of physical-design platforms. This may be because 2.5D solutions look like miniature package substrates that then get inserted into other more-conventional package substrates. Therefore, from an EDA tool perspective, this can appear much more like a stacked-die package design rather than a physical design on silicon. What has not been clearly demonstrated is the solution for 3D-IC in ASIC designs, by a major EDA tool company. This would appear much less like a stacked-die layout and more like a physical design, so there is still some more evolution needed in the tool space to address this 3D-IC technology. Critical steps such as LVS (layout versus schematic) checking still have limitations with this technology. In addition, timing analysis of nets between chips in this space is further complicated by the TSV connections and routing on different die without signal buffering.
Most sources agree that 3D-IC will not likely be mature enough for wide adoption for another two years or so in the ASIC space. On the other hand, 2.5D is much further along with regards to EDA tool readiness, likely due to the silicon-interposer's similarity to an embedded package substrate.
Figure 2. Short flat microbumps. Source: KK Tzu, ITRI, RTI 2010.
Figure 3. Short copper posts with solder. Source: E. Beyne, IMEC, RTI 2010.
Figure 4. Tall posts with solder tips. Source: P. Royannez, et.al., IME, RTI2010.
The good news here is that there are several interposer suppliers in the market enabling the 2.5D marketplace. The bad news is that their solutions are considerably different from one another and so are their cost structures. The major wafer fabs are keeping their cards close to their chest until clear standards emerge in order to avoid the expense of re-tooling at a later date. For those of us in the ASIC space, this poses some interesting questions. Either partner with new suppliers for early access to the technology or wait until the major industry players open their doors with standard design kits. Only a select few are being given a sneak preview of the incomplete design kits as early adopters. The rest either end up waiting by the sidelines or partnering with the select few able to access these design kits.
Probing of the tiles that interface to the silicon interposer or 3D-IC die cannot be done with conventional vertical-probe or cantilever probe technology. After all, these microbump pitches of 30 to 80Ám are too tight for these conventional approaches. Instead, several companies are devising new families of probe cards, which are generally based on MEMS technology. This means that the up-front cost for a probe card may go up considerably. MEMS probe cards have been available for some time, but the finer technology needed may make these a little more difficult to manufacture and maintain. The production cost structure here is not well understood yet, but at least a solution exists.
Assembly is one of the hurdles that has been addressed, but unfortunately there is little uniformity in how this is done. Some solutions in the wafer-to-wafer (W2W) format utilize a multitude of bonding techniques, but in the ASIC space, this should not be a major concern. It is unlikely that W2W bonding will be used in ASICs other than embedding stacked memory die in a 2.5D or 3D ASIC solution. At this point, the wafers are already bonded to each other and will likely be delivered by the memory suppliers in tape-and-reel format.
The two options for ASIC assembly of TSV devices will be die-to-wafer (D2W) and die-to-die (D2D), but I expect D2D to be the prevalent format for ASIC solutions. The reason I expect D2D to be the dominant format for ASIC assembly is that this allows the greatest flexibility of what to put on the TSV wafer, and it also eliminates the difficult thin-wafer handling. Wafers with TSV will be somewhere in the 50- to 150-Ám thick range, and, if given the option, the assembly sites would surely opt for the more robust D2D solution.
There are no clear assembly standards. Standards are being initiated for wafer handling as well as reliability, but assembly still has a hole in standards coverage. For example, some TSV technologies have copper posts with solder on the end, others have round bumps, while others may have relatively flat connections that are meant for having copper posts on both die in order to form the interconnect. Examples of these can be seen on the lower three images in this post. The assembly for these different formats may require different assembly strategies that may not be easily mixed. In addition, the gap between the die may be different resulting in different under-filling (plastic gap-filling between the die) materials and methodologies. In order to have multiple die capable of assembly on the same 2.5D or 3D-IC device, the assembly processes need to be compatible. At the moment, ASSP and FPGA providers design all of the die in the package, but this may not be the case in the ASIC space. For this, standards will be required to enable this technology for those of us the in ASIC realm.
JEDEC's JC-14.3 committee is working on the reliability standards required for this technology. This will clearly address concerns currently preventing wider adoption of the technology. Having standards that clearly define reliable packaging will help us all, so we are looking forward to the output of this committee.
Shipment of TSV wafer and die
Semi and Sematech have been working on standards primarily for handling these delicate TSV wafers and die. The current directions include bonded wafers, bare die, W2W attachment methods, etc. These standards normally take about a half-year to release, so expect to see the fruit of this effort towards the middle of 2011. This happens to coincide with the expected release of the wide-IO memory standard being developed by JEDEC. This means that the end of 2011 should see a significant flurry of activity.
By Javier DeLaCruz.
Javier DeLaCruz is the manufacturing technology director at eSilicon Corp. He is responsible for all package engineering activities including design, package selection, electrical extraction and simulation, co-design activities with the physical design teams, and system-level integration.
This article is based on an entry on Javier DeLaCruz's Package Matters blog.
Go to the eSilicon Corp. website to learn more.