| Introduction to SVA Assertions for Design Engineers | Publication: Design & Reuse
Contributor: Cyclic Design, LLC
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March 10, 2011 -- Assertions and assertion-based verification (ABV) are a hot topic, but many engineering teams remain unfamiliar with the benefits that assertions bring to the design and verification process. This article discusses the rationale for using assertions, the benefits of using assertions throughout the design and verification process, and a step-by-step approach to implementing assertions within a design.
This article is written from the viewpoint of a design engineer. Hopefully both design and verification engineers will see the relevance of (and humor in) these comments from the designer-centric world view.
By Eric Deal. (Deal is with Cyclic Design, LLC.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
Read more about
Cyclic Design, LLC
on SOCcentral.com |
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, formal verification, assertions, assertion based verification, assertion-based verification, ABV, SystemVerilog Assertions, SVA, Cyclic Design, Design & Reuse,
| | 599/33396 3/10/2011 1373 196 | |
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| | 0.1572266 |
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