| Hardware Co-Verification Using VMM HAL-SCEMI | Publication: Design & Reuse
Contributor: eInfochips, Ltd.
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March 10, 2011 -- Having SoC for HDTV under verification, verifying different components of SoC at block level are so far satisfactorily done using simulation. Now having full chip level environment and running simulation for few frames takes huge amount of time. To locate deep issues one need to run for multiple frames, this could run into system limitation. Hardware acceleration allows verification engineers to speed up verification and achieve early validation too.
This article talks about VIP architecture requirement for achieving hardware accelarated verification using on board generation, error checker, data checker and coverage collection, taking example of AHB synthesizable VIP.
By Dilip Sutariya and Jigar Patel. (Sutariya and Patel are with eInfochips, Ltd.)
This brief introduction has been excerpted from the original copyrighted article.
View the entire article on the Design & Reuse website.
Read more about
eInfochips, Ltd.
on SOCcentral.com |
| | Keywords: ASICs, ASIC design, FPGAs, field programmable gate arrays, FPGA design, EDA, EDA tools, electronic design automation, verification IP, intellectual property, cores, Verification Methodology Manual, VMM, eInfochips, Design & Reuse,
| | 599/33397 3/10/2011 2535 186 | |
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| | 0.15625 |
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