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System Awareness Improves SOC Power Management  
Publication: EE Times Power Management Designline
Contributor: AppliedMicro Corp. (AMCC)
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March 18, 2011 -- Reducing the power consumption of SOCs (system on chip) has become increasingly important in electronic system designs, even when there are no batteries involved. Improvements in device-level methods are one step in the enhancement of SOC power management. Adding system and application awareness, however, can amplify the effectiveness of those efforts significantly.

The benefits of power management in battery-operated systems are obvious. The lower the average power consumption, the smaller, lighter, or cheaper the battery can be. When using stock commercial batteries, lower power means longer operating life. Either way, lower power translates to greater customer satisfaction.

Increasingly, however, power management is becoming critical in line-powered systems as well. Managing system power consumption yields multiple benefits. In data centers, for instance, the server farms are seldom fully loaded, yet never completely off. As a result, they can consume nearly half their total power simply idling.

By Satish Sathe. (Sathe is Senior Systems Architect, AppliedMicro Corp.)

This brief introduction has been excerpted from the original copyrighted article.


View the entire article on the EE Times Power Management Designline website.

Read more about
AppliedMicro Corp. (AMCC)
on SOCcentral.com

Keywords: ASICs, ASIC design, EDA, EDA tools, electronic design automation, power analysis, power optimization, power management, AppliedMicro Corp. (AMCC), EE Times Power Management Designline, system-on-chip, SoC,
599/33518 3/18/2011 1042 156


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