April 1, 2011 -- We are seeing an increase in technological innovation at phenomenal rates, despite any economic aftermath. Of course, this brings new (and sometimes near impossible) design requirements for our "smart" devices. This chain reaction translates to semiconductor companies demanding more of everything — better performance, higher levels of integration, increased graphics, 3D, 4G, extended battery life and the ability to connect to other devices. We want our smart phones and tablets to run multiple applications simultaneously — be on a call and search the web, have better graphics, VoIP and video calling. Our smart devices now require a "smarter" design approach, which begins with how we select and integrate IP.

In order to meet the end customer demands, these devices need to be smaller, cheaper and faster, and first to market. We already have multicore CPUs, GPUs, DSPs, video and audio codecs, with more on the way. So with innovations around every turn, how can SOC designers attempt to keep up? Will traditional SOC design methodologies be good enough to succeed moving forward?

Given these demands, IP selection and integration has become a critical piece of the SOC design puzzle. IP selection is no longer relegated to selecting a few I/O blocks. Entire end-to-end system functions, including software, are now being purchased from third-party IP vendors, making up a large percentage of the entire SOC. According to recent Semico Research data, there will be an average of 70 unique IP cores in each SOC in 2012. Keep in mind that this is only an average; we will also see SOCs in excess of 100 unique IP cores in many next-generation designs. We expect that nearly half of these designs will be 65nm and smaller. So as 2012 production devices are now being designed, it is imperative that companies find more efficient ways to manage and integrate all their IP.

Having the ability to quickly identify and integrate IP will be a clear way for companies to differentiate their products. Purchasing IP was traditionally a way to supplement your own internal IP, while still retaining a unique "niche" or value-add to differentiate a product (e.g., faster, lower-power, better software). With the chip density that today's process technologies offer, companies can pack so much functionality onto a single die that it becomes very difficult for any single company to invest in and develop all the IP necessary. In addition to the IP investment, new technologies are spawning 3D chips (Through-Silicon Via – TSV) with a wide I/O interface to manage the amount of memory bandwidth required in smart devices. Although these technologies have their physical-design, process and testing challenges, mastering all these simultaneously is fundamentally the best way to keep pace with the demands of end applications.

So where do SOC designers begin, and how can they take advantage of the rapid advancements in IP and process technologies? On the flip side, what are IP vendors doing to make this arduous task easier? Traditionally, choosing the processor and key IP blocks such as DSPs and GPUs have been the usual starting point, but how these blocks are combined with the others in the system and how they will interact with applications software is a critical part of today's design process. This methodology is not optional when performance and time-to-market goals are on the line. Simply choosing the fastest processor and the most efficient DSP will not be good enough anymore if the overall system cannot keep up with the performance.

To help ease the task of IP selection, Sonics and others are building complete subsystems to further ease design and cost burdens — to the point where a single IP block can now serve as the entire subsystem. By combining several synergistic IP blocks into a single product, the overall IP selection and evaluation for the designer is dramatically reduced — and also allows the IP vendor to optimize the performance of these blocks. For example, combining a memory controller and PHY with a memory scheduler will provide a highly tuned turnkey, memory subsystem optimized for the highest DRAM utilization — with the best possible performance/ area result on-chip for a given application.

Taking this even farther; combing the memory subsystem with the system interconnect, the network now provides end-to-end support from the processors to the DRAM and to the I/O. Leveraging this complete network will ensure that system performance is achieved and all devices are communicating efficiently with DRAM and I/O. You can also add programmable registers to this network, which will allow higher levels of hardware visibility by the software for tighter and perhaps even "virtual" control of functions — such as the memory subsystem and power management. We are even starting to see new subsystems that combine the processor, graphic chips, video subsystems and audio subsystems.

When selecting and integrating IP, the subsystem approach will ultimately strengthen the designers' position to work with new technologies as they emerge. Integrating memory interfaces like wide I/O now falls heavily on the memory IP subsystem provider. So now SOC designers will be able to take full advantage of the increased bandwidth and reduced power that wide I/O promises to deliver — without the overhead of designing these new IP blocks internally.

Without a doubt, IP suppliers have to be aware of, and consider, the total system as they team with semiconductor companies. Subsystems are a solid start, but how these subsystems are combined will have a significant impact on the overall system performance. The "brute-force" method of over-provisioning the system for worst-case scenarios is becoming expensive not only in die area, but power dissipation.

On-chip network IP providers are uniquely positioned to drive this end-to-end system control since the network touches every IP block in the system. Selecting the right IP and connecting the IP blocks on-chip is no small feat, and one of the most challenging elements of SOC design. We are now seeing IP companies rise up the "SOC food chain" with the acknowledgement that their solutions have broad and powerful implications for easing system complexity and cost. Because of this newly heightened value-add, SOC designers are now increasingly teaming with IP companies early in the design process to help them manage on-chip traffic, hit performance goals and intelligently integrate all their third-party IP on-chip. Today, IP is no longer an afterthought.

By Frank Ferro.

Frank Ferro is the Director of Marketing for Sonics, Inc., responsible for the company's complete portfolio of on-chip network IP products. Ferro has over 25 years of experience in the semiconductor industry and has worked extensively in the communications and consumer electronics fields, with expertise in the areas of WLAN, Voice-over-IP, cellular phones, personal computers and SOC architectures.