April 7, 2011 -- One of the challenges for present SOC designers is to ensure that their SOCs consume the least power. Since almost all SOCs use a set of IPs, it's important for the IP providers to give different power-reduction options in their IPs, enabling the SOC designers to design power-optimized chips. This article primarily focuses towards IP design and verification engineers and lists some useful power reduction features that can be implemented in an IP.

The USB IP core is used as an example to demonstrate how the USB functionality can be segregated into different functional states and how a combination of power features can lead up to 97% reduction in total power and 96% reduction of leakage power.

By Sayandeep Nag, B.U. Chandrashekar and K.D. Prathima. (Nag and Chandrashekar are wtih Synopsys, Inc. and Prathima is with the Manipal Center for Information Science, Manipal, India.)