May 31, 2011 -- Mentor Graphics Corp. today announced that the high-level synthesis tool now supports the synthesis of transaction-level models (TLMs). TLM synthesis provides the foundation for an executable methodology allowing interplay between Catapult C Synthesis and the Vista platform, resulting in a complete TLM 2.0-based solution for virtual prototyping and hardware implementation and enabling the creation of synthesis-ready virtual platforms.

Expanding its full-chip synthesis technology, the Catapult C tool now delivers a methodology and a set of models to support TLM synthesis. With the new TLM synthesis flow, abstract TLM models are converted to pin-accurate, protocol-specific, SystemC models, and from there, synthesized to RTL code. Conversely, existing synthesizable descriptions can be converted to TLMs. The flow supports standard off-the-shelf bus interfaces, including the ARM AMBA bus family, as well as custom protocols.

This new capability provides an essential link between virtual prototyping and HLS-based hardware implementation. Traditionally, these two activities have been separated by incompatible abstraction requirements: virtual prototyping relying on fast and abstract TLM interfaces, and HLS requiring pin-accurate synthesizable models. With its new TLM synthesis capabilities, the Catapult C tool closes this gap and, combining with Vista, opens new opportunities in ESL design, verification and virtual prototyping.

"Eighty-seven percent of the respondents in a recent survey said it was either mandatory or highly desirable to have high-level synthesis tools integrated with ESL flows," said Simon Bloch, Vice President and General Manager, Design and Synthesis division at Mentor Graphics. "TLM synthesis leverages Mentor’s strong technology ‘know how’ in both high-level synthesis with Catapult C and virtual prototyping with the Vista platform as a pivotal starting point for new levels of ESL flow integration."

Synthesis-ready virtual platforms leverage standard TLM interfaces to combine simulation and synthesizable models. This allows joint design and verification at both the platform and the IP levels using a single and consistent ESL model. Hardware design teams can create abstract TLM models to be automatically synthesized to production quality RTL code using the Catapult C tool. At the same time, those models can be shared with the platform team for system integration, early software testing and fast ESL verification using Vista. Uniting TLM synthesis and simulation effectively creates convergence of ESL models and flows.