May 19, 2011 -- Successful low-power IC designs implement several power-management schemes through a comprehensive design, implementation and verification tool chain that understands the power intent. These designs include a large portion of embedded memories that may dominate the chip's power allocation. Minimizing power while maximizing performance and density are the primary focus for today's SOC designers that are challenged with the increasing embedded memory count driven by the rich A/V content in today's consumer products.

This article addresses minimizing low-power design complexity with power, performance and density optimized IP. It covers the power problem, and the complexity of designing with multiple power domains in SOC designs that contain embedded memory. The article includes the trade-offs and benefits of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning.

By Lisa Minwell. (Minwell is with Synopsys, Inc.)